The challenge in producing silicon carbide/silicon, particularly 3-step cubic silicon carbide (3C—SiC) and Si heteroepitaxy, is the tensile stress introduced at the Si/SiC interface due to the lattice miss-match between the two materials and the faster thermal contraction of SiC while cooling down from the typical growth temperature of 1370° C.
It has already been demonstrated that dividing the surface of the wafer into sub-die of the order of 2.5 mm per side with thin lines of polycrystalline SiC is beneficial in terms of reducing the wafer bow induced by these tensile stresses.
It is an aim of the present invention to reduce the wafer bow using an efficient technique.